How the RISC-V architecture’s inherent traits align with the demands of functional safety standards like ISO 26262.
The ISRO Inertial Systems Unit (IISU) in Thiruvananthapuram initiated the development of a 64-bit RISC-V-based controller and ...
New Delhi: Indian Institute of Technology (IIT) Madras and ISRO have developed an indigenous microprocessor for space ...
IIT Madras develops indigenous Shakti semiconductor chip for ISRO, marking a milestone in Make in India efforts.
A new technical paper titled “Optimizing Energy Efficiency in Subthreshold RISC-V Cores” was published by researchers at Norwegian University of Science and Technology (NTNU). Abstract “Our goal in ...
Collaboration milestone addresses key pain points of typical design verification, the open silicon ecosystem organisation, ...
IIT Madras and ISRO developed and tested the SHAKTI-based IRIS chip for aerospace applications, promoting indigenized ...
(GLOBE NEWSWIRE) -- lowRISC C.I.C., the open silicon ecosystem organisation, today announced the addition of formal ...
IIT Madras and ISRO have collaboratively developed the SHAKTI microprocessor for space applications. This indigenous chip, based on RISC-V architecture and backed by the Ministry of Electronics, aims ...
IIT Madras and ISRO collaborate to develop SHAKTI-based semiconductor chip for indigenous microprocessor products with RISC-V technology.
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